1. Field of the Invention
The present invention relates to a method for forming an insulating film, a method for forming a multilayer structure and a method for manufacturing a semiconductor device. More particularly, the present invention relates to a method for forming an insulating film using low dielectric constant insulating materials (Low-k materials), a method for forming a multilayer structure using the insulating film, and a method for manufacturing a semiconductor device having the multilayer structure.
2. Description of the Related Art
In a multilayer wiring structure widely used currently in constructing a semiconductor device, a propagation speed of signals is determined mainly by a wiring resistance and a parasitic capacitance of an insulating film which is present between wirings. When a wiring interval is equal to or more than 1 μm, a capacitance between adjoining wirings is small and has a small effect on a speed of the whole device. On the other hand, when the wiring interval is about equal to or less than 0.5 μm, the capacitance between adjoining wirings has a larger effect thereon. In particular, according to the future assumption, a circuit may be formed at a wiring interval of equal to or less than 0.2 μm. In such a case, it is expected that the capacitance between adjoining wirings has an extremely large effect on the device speed. Further, a high integration in the semiconductor device proceeds in recent years and therefore, the wiring interval is made narrower. As a result, the capacitance between adjoining wirings increases if the wiring thickness is the same as heretofore. Accordingly, when reducing the wiring thickness to decrease a region of an insulating film between wirings, the capacitance between adjoining wirings can be reduced.
However, when reducing the wiring thickness, the wiring resistance increases and as a result, speeding up of a circuit operation is prevented. Accordingly, it is nowadays considered that the most effective method for attaining reduction in the capacitance between adjoining wirings is to allow a lower dielectric constant of an insulating film used. From that point of view, low-k materials having a dielectric constant of about 2.0 to 2.5 are taken notice of.
For one method for forming the insulating film (Low-k insulating film) using the Low-k materials, a so-called spin-on process is used. The spin-on process is a process as described below. A precursor solution formed by dispersing Low-k materials in a solvent is coated on a predetermined substrate by a spin coating method to form a coating film. The coating film is heated at a temperature near a boiling point of the solvent to remove the solvent (a baking process). Then, the coating film is further heated at a higher temperature for a given length of time. As a result, the coating film is sintered to form a network structure where molecules within the Low-k materials are cross-linked (a curing process). Thus, a Low-k insulating film is formed.
When forming the multilayer wiring structure using the spin-on process, the following method is used in many cases. The method comprises, for example, the steps of: forming a lower copper (Cu) wiring as a conductive material by a damascene method, forming thereon a diffusion barrier film for preventing copper diffusion by a CVD (Chemical Vapor Deposition) method, forming a Low-k insulating film as an interlayer insulating film by the spin-on process, forming an etching stopper film (a middle stopper film) or a cap film using the CVD method again, and forming within the Low-k insulating film a via which communicates with the lower copper wiring, or an upper copper wiring. At present, the diffusion barrier film as well as the interlayer insulating film is required to have a lower dielectric constant. Therefore, the diffusion barrier film is now formed using silicon nitride (SiN) or silicon carbide (SiC), particularly, SiC having a small oxygen content.
However, when forming the Low-k insulating film on the diffusion barrier film formed using such materials, there arises a problem of adhesion between the diffusion barrier film and the Low-k insulating film. In order to cope with the problem, the present inventors have made a study and found the following fact. When exposing the Low-k insulating film to hydrogen plasma after the step of forming the Low-k insulating film and before the step of forming the etching stopper film, the adhesion between the diffusion barrier film and the Low-k insulating film can be improved.
Further, in the multilayer wiring structure, minute wirings are generally used for the lower layer in many cases. In such a case, the above-described problem of the capacitance between adjoining wirings becomes more significant and therefore, it is strongly desired that the Low-k materials are used particularly for such a portion. On the other hand, in the portion where the minute wirings are used, the capacitance between adjoining wirings in the upper and lower layers also becomes important due to expansion of an electric field. Accordingly, the necessity of providing the Low-k insulating film not only between lateral wirings but also between vertical wirings increases at present.
In addition, as an example of using plasma as described above in the formation of the multilayer wiring structure, the following method is heretofore proposed. The method comprises the steps of subjecting a surface of the copper wiring formed by the damascene method to a cleanup treatment with ammonia plasma and depositing thereon SiN while keeping a vacuum condition (see, Japanese Unexamined Patent Publication No. 2001-291720). Further, this proposal discloses that the adhesion between a copper wiring and a silicon oxide film which is present between the copper wirings is improved by thus treating the surface of the copper wiring with ammonia plasma.
However, in the spin-on process for forming the Low-k insulating film, a heat treatment such as a baking treatment or a curing treatment is required as described above. In particular, the curing treatment occupies a considerable amount of the time necessary for the heat treatment.
The curing treatment is usually performed at a temperature of about 400° C. in an inactive atmosphere. In the curing treatment, the following disadvantages are normally found. Depending on the treating time during the curing treatment, a mechanical physical property of the Low-k insulating film is affected, or adhesion between the Low-k insulating film and the underlying film where the Low-k insulating film is formed or the etching stopper film formed on the insulating film is reduced. The curing treatment is performed using a method of treating wafers in a single-wafer type using a hot plate or a method of collectively treating a plurality of wafers (e.g., 25 sheets) using a furnace. Among these methods, the method of treating wafers in a single-wafer type using a hot plate is disadvantageous in that a long period of time is required for treatment of a plurality of wafers. In that respect, the method of collectively treating wafers using a furnace is more advantageous.
However, also in the method of collectively treating wafers using a furnace, the heat treatment at about 400° C. for about 60 minutes is required. In addition, accompanying the heat treatment, it becomes necessary to carry wafers in the furnace, to carry wafers from the furnace to the outside, to displace atmosphere within the furnace and to lower or raise the temperature within the furnace. As a result, the curing treatment requires about from 90 to 120 minutes in total or may require much more time in some cases.
Further, the method of collectively treating wafers using a furnace has a problem that a temperature distribution within the furnace is normally nonuniform. Therefore, heat is nonuniformly applied between wafers or within a wafer surface particularly when the wafers increase in number or in size. As a result, it becomes difficult to form the Low-k insulating film uniformly.
In addition, when a large-sized furnace capable of collectively treating a plurality of wafers for the spin-on process is introduced in preparation for increase in size of wafers, massive plant investment is made, and therefore, it is not preferred. Further, even when introducing the large-sized furnace, there still remain the above-described problems that a long period of time is required for the curing treatment or the temperature distribution within a furnace is nonuniform.
Accordingly, when the spin-on process is performed without introducing new facilities and the time required to perform the process can be shortened, the process cost can be largely reduced. Further, the time required for the whole process including the subsequent step of forming the etching stopper film to form the multilayer wiring structure can be of course shortened, so that the cost of the whole process can also be reduced. Further, when the uniform Low-k insulating film can be formed irrespective of the number or size of wafers, the multilayer wiring structure having high quality and high performance, and the semiconductor device having the multilayer wiring structure can be effectively formed at low cost.